Tasks:
- * Analyze and optimize bandwidth, latency, and power
- * Assess performance trade-offs across area, power, and performance
- * Debug interface, CDC/RDC, timing, and software configuration issues
- * Define DMA, buffers, registers, interrupts, and debug
- * Define SoC subsystem solutions and microarchitecture
- * Design IP datapaths and control paths
- * Design IP wrappers and interface adapters
- * Develop architecture and integration specifications
- * Evaluate and configure third-party IP
- * Integrate clock, reset, power, security, and debug infrastructure
- * Integrate IP with SoC fabric and memory subsystem
- * Partition multimedia and perception modules
- * Plan verification and support integration closure
- * Review RTL design quality
- * Support tapeout and silicon bring up
Perks/Benefits:
Skills/Tech stack required:
[AHB] [APB] [Area Optimization] [ASIC design] [AXI] [Bandwidth analysis] [Buffer sizing] [Camera Pipelines] [CDC/RDC] [Clock and reset design] [DisplayPort] [Display processing] [DMA] [DSP Accelerators] [EDP] [IP integration] [ISP] [Memory subsystems] [Microarchitecture] [MIPI] [Multimedia datapaths] [NOC] [Performance Power and Area] [Performance, power, and area optimization] [Power and area optimization] [Power Domains] [QoS] [Register Interfaces] [Reset design] [RTL] [SoC Architecture] [SoC integration] [SystemVerilog] [Verilog] [Video codecs]
Educational requirements:
N/A
Role(s):
[ASIC Design Engineer] [Design Engineer] [Engineer] [Integration Engineer] [Microarchitecture Engineer] [SOC Engineer] [SOC Integration Engineer]