Tasks:
- * Advise on design-for-synthesis improvements
- * Develop and manage SDC constraints
- * Optimize timing, area, and power
- * Perform RTL-to-gate-level logic equivalence checks
- * Perform RTL-to-gate-level logic synthesis
- * Resolve setup and hold violations
- * Resolve timing bottlenecks with physical design teams
- * Troubleshoot clock domain crossing issues
Perks/Benefits:
Skills/Tech stack required:
[Cadence Genus] [Circuit design] [Clock Domain] [Clock Domain Crossing] [Clock domain crossing analysis] [CMOS device principles] [Conformal] [Design Compiler] [Digital circuit] [Digital circuit design] [Equivalence checking] [Formality] [Fusion Compiler] [Linux] [Logic equivalence] [Logic equivalence checking] [Low power] [Low power design] [Perl] [Power design] [Python] [SDC] [Shell Scripting] [Static Timing] [Static Timing Analysis] [Synopsys Design Compiler] [Synopsys Fusion Compiler] [SystemVerilog] [TCL] [Timing Analysis] [Timing closure] [UPF] [Verilog]
Educational requirements:
[Doctoral degree]
Role(s):
[Digital IC Synthesis Engineer] [Engineer] [Logic Synthesis Engineer] [Synthesis Engineer]